HMC832 : Locking time

Document created by analog-archivist Employee on Feb 23, 2016
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We are working  on a frequency hopping system. And we use HMC832 Eval kit to
understand HMC832 is  suitable or not  for our applications. So one of  the
most  critical issue on our application is phase noise. Phase noise seems quite
enough. And also locking times are very important. So We want to measure
locking times when frequency is hopped to another frequency. Lock detect and
SDO are common. So How did you measure locking times which you mentioned in
your datasheet? Could you suggest measuring method for locking times? And
ADISIMPLL simulation tool gives locking times. Is ADISIMPLL's outputs


The ADIsimPLL tool gives an approximate lock time but it is not very accurate. 
The value could be out be a factor of x10.  To measure lock time they need a
tool like the Keysight E5052B which measures how long the PLL takes to lock the
output phase within a specified value.  For example the time to hop from 3G to
2G and settle within 10° (difference between output phase and reference) is
140us for the following measurement: