Pullup voltage for port 1 signals diferent from Vdd1

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

I plan to power port 1 at 3.3V. But I need to interface to a Xilinx Virtex-6
FPGA. I wonder if setting a 2.5V voltage for the SCL, SDA signals in port 1
would work or if it would produce overcurrents somewhere.

 

This configuration will not damage any parts on the bus. As long as the VIL is
compatible with your output, you can do it. The pull-ups would simply be
referenced to the 2.5V supply.

Attachments

    Outcomes