ADuC845: Silicon revision and anomaly sheet

Document created by analog-archivist Employee on Feb 23, 2016
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1) Which silicon revision is currently shipping for ADuC845?
2) In "Anomaly Sheet for Silicon Rev. C ADuC845" it says that ADC noise
performance degrades when CD < 3. Will this be corrected in future silicon
revisions? If so, when can such revisions be expected? If not, can you
specifiy/quantify how the performance is degraded with CD=0 and 1 for 5V
operation? 

 

Please find the answer to your questions below.
1) Which silicon revision is currently shipping for ADuC845?
1. The silicon currently shipping is Rev C.

2) In "Anomaly Sheet for Silicon Rev. C ADuC845" it says that ADC noise
performance degrades when CD < 3. Will this be corrected in future silicon
revisions? If so, when can such revisions be expected? If not, can you
specifiy/quantify how the performance is degraded with CD=0 and 1 for 5V
operation?

2. The ADC noise errata relates to a potential (and I stress the word
potential) case where due to code the ADC clock and the core (instruction)
clock on the fast sigma-delta parts can coincide causing excessive digital
noise in the part.
Ideally the ADC and core clocks are delayed relative to one another to minimize
noise, however due to the nature of the fast core scheme this delay is
dependant on the number of instructions used around and during the ADC loop of
the program. Unfortunately this is extremely difficult to quantify (i.e. in
terms of the exact number of instructions and is very dependant on the
application). The one thing I would say is that in general a customer will
probably not see this issue. So far, with all the ADuC845/7/8's in circulation
no-one has reported this issue. We have been able to see it in the lab under
ideal conditions and when explicitly looking for it, but otherwise it is
difficult to reproduce.

The degradation can be varied if the condition is seen and depends on
the
relationship between the ADC and core clocks that are themselves dependant on
the instructions being executed. The attached plots show a typical example of
the type of response seen at CD=0 and CD=1 when the issue can be seen. This is
by no means exactly what a customer will see. This is what we could see on our
test setup given the conditions under which we tested it.

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