ADuC845 interrupt priority handling

Document created by analog-archivist Employee on Feb 23, 2016
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A few questions question regarding ADUC845 interrupt system:

Q1. A high priority interrupt can interrupt the service routine of a low
priority interrupt, Does the system comeback to service this low priority
interrupt
later?

Q2. If two interrupts of the same priority level occur simultaneously, the
polling sequence, Q Could you explain how this work please. Do we have queue?

 

Answers to questions regarding interrupt priority on ADuC845:

Answer 1. A high priority interrupt can interrupt the service routine of a
lower
priority interrupt and yes the 8052 core will come back to service the lower
priority
interrupt.

Answer 2. If two interrupts of the same priority level occur simultaneously,
the interrupt
source with the lower vector address will be serviced first. For example, Timer
0 interrupt
will be serviced before the ADC interrupt. Asserted IRQ sources are serviced in
sequence.


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