ADuC84x, tolerance of PLL output frequency

Document created by analog-archivist Employee on Feb 23, 2016
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I am using ADUC843 with 32768 Hz crystal. The PLL is configured as it generates
16,78Mhz output. What is the tolarance of PLL output frequency?

 

The ADuC84x PLL will generate exactly 512 core clock cycles for each input
clock cycle from the 32768Hz crystal. The average frequency is therefore
exactly 512 times the XTAL frequency and is therefeore determined by the
frequency error on the XTAL.
The PLL will introduce a small amount of random jitter but this will not be
significant in the operation of the device. If the PLL is allowed to operate in
free-running mode i.e. there is no external crystal connected, then the
tolerance of the clock core frequency is +/-20%.

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