QWhat external clocks can be used with the ADuC834? Can the PLL be bypassed?
AThe PLL circuit on the ADuC834 will lock to 384 times the input clock as long
as the clock
frequency is within the frequency range 32.768kHz ± 20%. The ADC incorporates
50Hz and 60Hz
rejection filters which assume a 32.768kHz input frequency. Using an input
clock that differs from
32.768kHz will cause these rejection filters to move.
Although it is possible to use the ADuC834 with an input clock other than
32.768kHz it is
recommended that you use a 32.768kHz clock/crystal to preserve the ADC
There is no mode of operation on the ADuC834 that allows the PLL to be
bypassed. Hence the
ADuC834 cannot be driven directly with an oscillator other than 32.768kHz