ADUC834: What is the minimum time (or ADC cycles) to get a reading if the input is a step? 

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

What is the minimum time (or ADC cycles) to get a reading if the input is a
step? 

 

Often confusing for our customers, because of the chopping scheme we use, the
full settling time through the ADC is 2 x tadc (see page 28 in the ADuC834
datasheet). This means that the time taken to a first conversion result is
twice the throughput time. This also means that if you change (or step) the
input then you will have to wait 2 full conversion times to see a valid output
or more correctly put is the settling time to an asynchronous step input will
not be reflected on the output until the third subsequent output ( because the
step change could happen in the middle of a current update cycle and you have
to wait 2 FULL cycles to see the settled result, result in 3 cycles in total.

Attachments

    Outcomes