Configuration for slow Flash devices

Document created by analog-archivist Employee on Feb 23, 2016
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The ADSP-TS201 EZ-Kit LITE works with SCLK = 5x 20MHz = 100 MHZ. After reading
the ADSP-TS201 Hardware Reference manual, we've found that the maximum number
of wait states in 'Slow Device Protocol' is 3. We understand that with 100MHz
SCLK and a 70ns Flash the number of required wait states is 7. Could you please
advise how to configure the interface with the slow Flash device for proper
operation?

 

You cannot access the FLASH via the /MS0 line with the slow device protocol
with an external clock frequency of 100MHz. The maximum programmable number of
wait states is 3. Thus, with the 70ns access time this would not be possible.

Therefore, you would need to slow the external port clock in order to be able
to respect the 70ns access time. Furthermore, please be aware that byte data
packing/unpacking from/to 8-bits to 32-bit words needs to be done in software.

Slowing the clock may not be a feasible option for some applications, so we
would recommend you to access the FLASH memory using the DMA engine in
conjunction with the /BMS line. For this, you would have to select "Prom Boot"
as the DMA Type. Using this method, the part access time as well as the data
packing/unpacking (data packing/unpacking automatically done by the DMA engine
for READ accesses ONLY) would be respected. This is the method used by the
processor when performing a boot from PROM.

One important point is the fact that the DMA engine will NOT perform the data
packing for you when writing to the FLASH device. This is only supported for
read accesses. Therefore, you would need to make sure the data writes to FLASH
are 8-bits wide. That is, you need to manually (by software) take care of the
data packing in your code. For more details on this, please refer to Fig.8-16
on page 8-34 in the External Port and SDRAM interface chapter in the ADSP-TS201
Hardware Reference (Rev 1.1,December 2004).

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