Core access of same variables at the ADSP-BF561

Document created by analog-archivist Employee on Feb 23, 2016
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Question about the dual core Blackfin Processor ADSP-BF561: if the 2 cores are
accessing the same variable, what happens ? or can each core run a different
independent program?

 

Each of the two cores can run different programs independent from each other.
Keep in mind that, as explained in the hardware reference manual, each core of
the ADSP-BF561 has three blocks of on-chip memory:

• L1 instruction memory
• L1 data memory
• L1 scratchpad RAM

Additionally, the ADSP-BF561 dual cores share a low latency, high-bandwidth
on-chip Level 2 (L2) memory. On-chip L2 memory is capable of storing both
instructions and data.

In cases where the same resource is shared between the two cores, semaphores
should be used. Please refer to the "Semaphores" section of the "System Design"
chapter of the ADSP-BF561 Blackfin Processor Hardware Reference.

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