duty cycle of the clock

Document created by analog-archivist Employee on Feb 23, 2016
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Does the duty cycle of the clock need to have the ratio of 1:1?
We want to generate a signal with 16,384MHz which looks like:

40,7ns > 10ns      25ns < 61ns < 100ns
|____|   ____    ____   |____   |____
|    |  |    |  |    |  |    |  |    |
|    |  |    |  |    |  |    |  |    |
--      --      --      --      --
|  |
20,35ns > 10ns

You can also see the values from the datasheet, so we are in spec.
But there is not mentioned how the duty cycle has to be.
I tried to run the BF539 with this clock, it works fine.
But I need to know if the above signal is ok?

 

your're right that you are in the specifications of the processor. From that
point there should be no problem with your clock.
Keep the same period of
the clock, because the PLL can't handle variing clock periods.

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