Count of Blackfin core clock cycles

Document created by analog-archivist Employee on Feb 23, 2016
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How can we count Blackfin core clock cycles? CYCLES and CYCLES2 don't seem to
count anything (their value is always zero!)

 

The reason the cycle counter does not see to be working is because it has not
been enabled. From the VisualDSP++ On-Line help: "To enable the cycle counters,
set the CCEN bit in the SYSCFG register.  The following example shows how to
use the cycle counter:

R2 =  0;
CYCLES = R2;
CYCLES2 = R2;
R2 = SYSCFG;
BITSET(R2,1); 
SYSCFG = R2;
/* Insert code to be benchmarked here. */
R2 = SYSCFG; 
BITCLR(R2,1);
SYSCFG = R2;
"

This works for both simulator and emulator.

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