How to handle the sequence in ADP5052?

Document created by analog-archivist Employee on Feb 23, 2016
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How to handle the sequence in ADP5052?


Each channel in ADP5052 has individual precision enable with 0.8V accurate
turn-on threshold, which allows one channel’s output can be tied to other
channel’s enable input (through optional RC delay timer) to well control
power-up sequence. The PWRGD signal can be used along with enable pin to
generate the sequence as well.

It is possible to create a rough power-down sequence by precision enable to
program different UVLO threshold for each channel, a delay time between
channels can be produced when input power supply plug out and discharged
slowly. Active output discharge feature helps the output capacitor discharge
quickly to well control power down sequence. Just be noted it is difficult to
produce the power-down sequence if the power supply discharges too quickly.