ADN2816: Which clock edge does the retiming block of the ADN2816 use to output data?

Document created by analog-archivist Employee on Feb 23, 2016
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Can you tell me which clock edge the retiming block of the ADN2816 uses to
data? I'm assuming from the datasheet that it uses the rising edge, and that
the output register has a propogation delay of around 0.74ns?


The ADN2816 re-timer circuitry will output the re-timed data at the middle of
the input NRZ pulse.
It will extract the clock embedded in the input data stream and use the clock
rise edge to sample the NRZ bit information.