ADIsimPLL_absolute frequency error-1

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Aug 10, 2016
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There is a question about the simulation software ADIsimPLL.
There is a plot about absolute magnitude of the frequency.
I think it reflects the locking time and the frequency error should be zero
when the PLL is locked. Do you think so?
But why it seems there is still an error after the PLL is locked?

 

This is caused by the OP-amp offset current and bias current, this is dead zone
of the OP-amp.
If op-amp offset current and bias current is ideally 0A, then PLL will lock
without any frequency offset.

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