SMPL_PRD setting of ADIS16365

Document created by analog-archivist Employee on Feb 23, 2016
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  The following customer of China meets a problem when setting the SMPL_PRD
register. It’s said from datasheet that SPI clock shouldn’t be faster than
300KHz if want to set it into “low power mode”(SMPL_PRD >= 0x0A). But from the
customer side, they can’t set this register bigger than 0x11 when the spi clock
is 125KHz. The 20ms’ sample rate(SMPL_PRD=0x23) is needed from them. Does the
clock need to be set lower as the SMPL_PRD being larger? Would you like give
some suggestion?


Are they using the ADISUSBZ? If that is the case, then it will limit this
setting because the SPI is set to 333kHz. They may want to set SMPL_PRD to
0x0001, SENS_AVG to 0x0404 and the read every 16th sample, if they want best
performance in the sensors. Just lowering the sample rate will under sample the
330Hz bandwidth and degrade the stability performance.