QI'm intending to use the ADG601 switch in a new design. The switch will be
powered from +/-5V supply rails ie. Vdd=+5,Vss=-5V. I ideally wish to drive the
ADG601 digital input from a FET (drain) and was intending to use a high value
pullup resistor to Vdd at the FET drain. Do you see any issue in doing this?
I'm not concerned about switching speed.
AI assume that what you want to do is to set the HIGH logic for the control
input using a high value pull-up while the LOW logic will be set using the FET
which will pull the control input to GND. If that is the case, I don't see any
problem, but you should be aware that having an excessively high pull-up could
make the control input of the switch more susceptible to pick-up noise as with
any CMOS logic device.