ADG3308: Design queries

Document created by analog-archivist Employee on Feb 23, 2016
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We try to use the AG3308 as Level Translator between a 3.3V-FPGA with IP-Core
for MC68HC11A1 and diverse 5V-I/Os at our different applications. 
Now there are some questions upcoming reading the datasheet. 

1. Input Driving: We measured switching at an input current of about 2mA,
required as in datasheet are 36mA. 
2. How is DataDirection at PowerUp? 
3. Can I use an input in parallel with an ADC-Input? ... and some more
questions in future?

 

Question 1;
This looks correct. But the architecture of the input requires the one Shot
detects a rising edge, and turns on the PMOS transistor for a short period of
time. To ensure this for all inputs, 36mA may be required.

Question 2;
With Vccy required to be powered up first, and also the EN pin being driven
from Vccy, then this is the default power up. But ,once both power supplies are
up , the device can be driven in either direction.

Question. 3;
I am not too sure about the third question. it would be best to buffer the ADC.
Any switching noise on the ADG3308 will inherently effect the performance of
the ADC. Buffereing the ADC will reduce switching noise on the ADC.

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