ADG3308 and indeterminate i/p o/p state's interface  query

Document created by analog-archivist Employee on Feb 23, 2016
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not sure what happens if both the input and output are in indeterminate
states. can you advise

 

We advise and use the En pin as the control to disable the ADG during
FPGA interafce startup. or use a pull-up on either side of the ADG to maintain
logic
level at one side.

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