QIs it possible to reduce the ADF7242's 664uS Receiver calibration time in
I am looking at using the ADF7242 for a proprietary Frequency Hopping radio
link. I would like to determine the blanking interval, i.e. how long it will
take to hop between frequencies.
Referring to the datasheet, Section Receiver Calibration in GFSK/FSK Mode on
page 60, the Frequency Synthesizer's totatl receiver calibration time is 664uS
(refer to Figure 94). This is two slow.
1) Is OCL calibration required before using a new frequency?
2) Is there any way of reducing calibration time (i.e. by using stored
AThe only calibration that isn't mandatory is the VCO calibration and this
should be required since the frequency will be changed.
The OCL time specified is based on the time required to minimize the offset on
entering RX from PHY_RDY state. We don’t have characterization data for just
changing channels while remaining in RX. If the residual offset is too high it
will impact sensitivity. I would suggest that the OCL calibration should still
be done but it may be possible to reduce the calibration time. The time allowed
for the offset calibration is programmed in Registers 0x3C0[7:4] ( course cal)
and 0x3C4 (fine cal). The attached spreadsheet has the formula to relate the
settings of these registers to offset cal time. They could try reducing
register 0x3C4 setting to 0x02.
It is possible to check the residual offset by doing ADC I and Q readbacks
(registers 0x3AE and 0x3AF [5:0] (signed, 2s complement)). There is some
repeatability spread on the ADC readback so it is better to average over
They would need the part to stay in RX and reissue the RX command after setting
the new frequency.