QReferring to the ADF7021-V datasheet revision A, figure 58 on page 44.
I am questioning whether or not the diode shown in figure 6 is actually shown
reversed. The ADF7021 always drives the clock TxRxCLK in both receive and
transmit modes. I therefore class the ADF7021 as SPI master.
In transmit mode data flows from microcontroller to ADF7021. The MISO (master
in, slave out) pin of microcontroller is blocked by the diode thus the ADF7021
will not see the incoming data.
In receive mode the ADF7021 pushes data at the microcontroller. In this case
the diode will conduct (assuming MISO is logic zero) and will most likely drag
the TxRxData line low because teh TxRxData and MISO lines will be fighting each
If the diode in figure 58 was rotated then I think all of these problems would
go away. Can you confirm or deny my suggestion?
N.B. I note the ADF7021 evaluation motherboard has the diode orientated as per
the datasheet, but it is quite feasible that the processor on the motherboard
may be getting around the diode orientation by tri-stating or otherwise it's
MOSI, MISO pins.
AYou are correct in your definition of master and slave in the system. The diode
is orientated as is in the datasheet and eval board to account for the state of
the pins when transmitting and receiving data. This orientation is specific to
the implementation with the ADuC84x microprocessor and may differ in your
The ADF7021, when receiving data from the uP, has a pullup on the TXRXDATA pin
and is in effect sourcing current to the uP. The uP toggles the MISO pin and
the current flows from the ADF7021 to the uP. When the ADF7021 is sending data
it is received by the uP in the MOSI pin.