Explain the ADF7021-N's DEMOD CLK and it's relationship with datarate and demodulator BW?

Document created by analog-archivist Employee on Feb 23, 2016
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Can you explain the ADF7021-N's DEMOD CLK and it's relationship with datarate
and demodulator bandwidth?

 

The DEMOD CLK is used to clock various parts of the demodulator circuit.

It is an internal clock divided down from XTAL reference. It needs to be set
between the limits in the datasheet (i.e. 2MHz ≤ DEMOD CLK ≤ 15MHz). Its value
will effect what datarate can be used as the CDR clock is divided down from the
DEMOD CLK.

The CDR CLK is taken from this DEMOD CLK (CDR CLK = (DEMOD
CLK/CDR_CLK_DIVIDE)). The CDR clock needs to be 32x the required datarate. So
this where the CDR clock is related to the Datarate and the demod clock is thus
indirectly related to the datarate.

The CDR_Clk has to be 32x the datarate. So the relationship is basically (by
putting two formulas for CDR and demod divide together):

DataRate=XTAL/(CDR_DIVIDE x DEMOD_DIVIDE x 32)

The DEMOD clock is not linked to the Tx Fdeviation. It is however linked to the
demodulator bandwidth in the formula for the discrimator bandwidth
(DISCRIMINATOR_BW = (DEMOD CLK * K)/400*10^3. The  DEMOD clock should be kept
within the limits set in the datasheet. There should be no need to go outside
these limits even at a low datarate .

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