Using ADF7020's Evalboard, the DATA CLK output is different to that indicated by S/W?

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Aug 10, 2016
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I would like to program ADF7020 with a datarate of 1.2Kbps. Although using the
values of the registers provided by Analog Devices software, I do not have
the expected result!
On pin Data CLK, I see a clock 10.8KHz instead of 1.2kHz with the oscilloscope.

Attached you will find a screenshot of register values calculated.

 

There seems to be a Bug in the Software (Version 2.4 - June 2012).   
While the correct CDR_CLK_divide is calculated and shown under the Advanced
Demod button the register is not being set with the corresponding value.
The customer can click on the manual register edit button and program register
3 with 0x709093. Note the register setting on the front panel will not be
updated but they should see the clock at the correct frequency.

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