ADF4360_Fast Lock Timer

Document created by analog-archivist Employee on Feb 23, 2016
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I am using ADF4350 and having a query about fast-lock timer. In Page 22 of the
datasheet, it is said that “Note that the duration the PLL remains in wide
bandwidth is equal to the fast-lock timer/fPFD.” But in the following section
of FAST LOCK- AN EXAMPLE, fPFD=13MHz, the duration of wide bandwidth is 40us,
lock time=50us. It seems not to accord with “the duration the PLL remains in
wide bandwidth is equal to the fast-lock timer/fPFD.”

 

There are a few details to be considered on the fast lock section.
1) The VCO band select occurs first. This takes 80 us.
2) For PLL fast lock, the fast lock function increases the PLL loop bandwidth
by increasing the charge pump current to the maximum value. This value is
determined by the PFD, MOD and fast lock counter.
3) The remainder of lock time is comprised of the PLL settling while in narrow
(steady state) loop bandwidth.
The example ignores the VCO band select completely. (There is a datasheet edit
highlighting this about to release). So considering the 50 us.
TOTAL lock time for the PLL is 50 us. But the optimum period in wide bandwidth
mode is calculated as 40 us. So we need to instruct the PLL to remain in wide
bandwidth for 40 us.
So when the fastlock counter counts PFD cycles (1/13 MHz) x MOD value (65),
this gives 5us. To get to 40 us we have to multiply the 5us by 8 to get to 40
us.

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