ADF4350_improve franctional spur

Document created by analog-archivist Employee on Feb 23, 2016
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In my application,ADF4350 did not worked in expected RF frequency.
I'm sure SPI communication is  correct since R divided output can be viewed at
Initialization of ADF4350 setting: Fpfd = 16MHz,reference doble and div/2 used,
4GHz,MOD = 160 => A0h,INT = 250 => FAh,FRAC = 0
The registers setting as:
R5 = 00 C0 00 05
R4 = 00 89 01 B4
R3 = 00 04 80 63
R2 = 13 00 60 C2
R1 = 08 00 85 01
R0 = 00 7D 00 00
Would you like to check and find any bug.
Do the control software for the EVAL-ADF4350 can generate every register value?


You don't need to enable fast lock in register. And if the 16MHz reference
input duty cycle is about 50%, that is ok for CSR, so they don't need to enable
reference doublers and ref div/2 both.
So I recommend you to change register value as below:
R5 = 00580005
R4 = 00880034
R3 = 00040003
R2 = 000040C2
R1 = 08008501
R0 = 007D0000
our eval software can generate every register value, please see attached
BTW, if you need output step in 100kHz from 2.2G-4.4GHz, then you may find
50kHz/100kHz offset sub fractional spur or integer boundary spur very high in
some frequency. in this case I suggest you to design a narrow loop bandwidth.
for frequency range of 137.5MHz to 2.2GHz, you could use RF divider output. In
this case VCO step could be x2 or x4, x8, x16 of 100kHz, fractional spur will
be better attenuated.