ADF4350: Worst case time for Power up to PLL phase lock?

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

I am using ADF4350 for 1030MHz and 1090MHz application. I programmed the PLL
register for RF output stage disable with DB5 of Register 4. I wonder what is
the time when setting the bit to enable its output. There will be output as
soon as setting the bit to 1 or it needs to wait for the locking time – about
100us? And there is the same query about the time when power-down to power-up.

 

The worst case power up on the output stage is equal to the PLL lock time
excluding VCO band select. So if the normal lock time from one channel to
another is 130 us. Then the worst case lock time for output power-up from mute
is 130 – 80 = 50 us. If output dividers are enabled, then the output stage
powers up much faster, less than 10 us. But the worst case for this number is
determined by the loop filter, which if the VCO is pulled, then the frequency
jumps a little and has to settle.
Power-up to PLL phase lock is determined by the loop bandwidth, plus the
acquisition time of the loop filter. Using a 40 kHz filter, the lock time is
around 130 us. 80 us from the band select process, 50 us from the PLL loop
filter.
Just to be clear.
With the VCO powered up, and assuming a PLL loop bandwidth of 40 kHz, then the
worst case lock time is about 50 us.
With the VCO powered off, and keeping the same frequency, the lock time is
similar, about 50 us.
With the VCO powered off, and programming a new frequency (requiring band
select), the lock time is about 80 us (band select) plus 50 us (PLL lock time)
= 130 us.

Attachments

    Outcomes