QIn ADF4108, there are two sets of charge pump setting to implement fast
locking. But in ADF4350, just one set of charge pump settings, how does it
work? Do they have the same working principle or just same as CSR (cycle slip
reduction) ? Is it necessary to load R3 every time RF frequency changed? Can
you explain in more detail?
AThe fast lock implementation in ADF4108 and ADF4350 are totally different.
In ADF4108, the fast lock is achieved by changing the charge pump current, so
the customer needs to program two charge pump settings, and program "CP GAIN"
to switch between the two charge pump settings (fast lock mode1), or setting a
timer to switch automatically after time out (fast lock mode 2)
In ADF4350, fast lock is achieved by changing the 'SW' pin to GND or high
impedance, so the customer needs to connect the SW pin to loop filter as in
topology in the circuits in attached word document. This could be simulated by
and customer needs to set timer value to do the automatic switch, this is the
same as ADF4108.
ADF4350 also supports CSR (cycle slip reduction) which could improve locking
time while loop bandwidth setting is too narrow (compare to PD frequency), it
turns on(or off) a constant charge pump current and forces the tuning voltage
to go in the right direction, and thus avoids cycle slip and improve locking
CSR function will work automatically, so you only need to program R3 one time
to enable this function. But there are two extra requirements to make CSR work
1. PD frequency needs to be 50% duty cycle. so if R counter is used, Ref div/2
also needs to be enabled to achieve 50% duty cycle;
2. ICP needs to set to a minimum value (0000)
Some of the registers and bits are double buffered, that means after you write
to these registers or bits, you have to write to R0 to make sure the part takes
these values into action.
For integer mode, the FRAC should be zero and you need to enable LDF bit to 1
to get integer lock detect.