ADF4108, ADF4350: fast lock mechanism

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Aug 10, 2016
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In ADF4108, there are two sets of charge pump setting to implement fast
locking.But in ADF4350,just one set of charge pump setting,how does it work? Do
they have the same working principle or just same as CSR ? Is it necessary to
load R3 every time RF frequency changed?Would you like to explain more
detailed.
How to use Double Buffer bit and LDF bit?

 

The fast lock implementation in ADF4108 and ADF4350 are totally different.
In ADF4108, the fast lock is achieved by changing the charge pump current, so
customer need to program two charge pump setting, and program "CP GAIN" to
switch between two charge pump setting (fast lock mode1), or setting a timer to
switch automatically after time out (fast lock mode 2)
In ADF4350, fast lock is achieved by changing the 'SW' pin to GND or high
impedance, so customer need to connect the SW pin to loop filter as below
topology (this could be simulated by ADIsimPLL):(see figure),and you need to
set timer value to do the automatic switch, this is the same as ADF4108.
ADF4350 also support CSR (cycle slip reduction) which could improve locking
time while loop bandwidth setting is too narrow (compare to PD frequency), it
turns on(or off) a constant charge pump current and force the tuning voltage go
with the right direction, and thus avoid cycle slip and improve locking time.
CSR function will work automatically, so only need to program R3 one time to
enable this function. But there are two extra requirement to make CSR work
correctly:
1. PD frequency need to be 50% duty cycle. so if R counter is used, Ref div/2
also need to be enabled to achieve 50% duty cycle;
2. ICP need to set to a minimum value (0000)

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