QI'm working on PLL synthesizer on frequency range up to 18GHz, I have gone
through the data sheet of ADF4106 , now i'm interested in working upto 18 GHZ
as so I found that in the frequency range from 13GHz to 18GHz the A and B
counter values of N divider are not satisfying the condition that B must be
greater than or equal to A.
AThe value of B must be greater or equal to A. Please refer to the attached
application note on PLL for the N counter structure. For the possible N value,
it should be in the range of
Nmin =(Bmin × P)+ Amin
=((P – 1) × P)+0
= P2– P
Nmax= (Bmax × P)+ Amax
Pls refer to the attached for the details. You can determine the B first to let
the N is between BP and (B+1)P and select the proper A afterwards.
I would recommend you use ADIsimPLL to simulate your design. The software will
give you the proper B and A value. The ADIsimPLL software can be downloaded
from ADI website.