QIs there any difference in phase noise performance when using different
pre-scaler values for the same N value? - Not measured any difference
AThe phase noise is primarily affected by the value of N, Charge pump current,
loop bandwidth and choice of VCO. We have not seen any difference in phase
noise for difference values of P for the same value of N.
At low output frequencies, the value of N can be realized in number of
different ways (N=BP+A). At higher frequencies you may not have a choice in the
value of the P as you are limited by the maximum clock speed of the CMOS A and
B counters (about 300MHz).
The ADF4106 uses an anti-backlash pulse to prevent dead zones in the PFD
transfer function and improve phase noise performance. The function of the
charge pump is to output current pulses proportional to the phase difference
between the R counter and the N counter. Even when the difference is zero (or
almost zero) the charge pump still outputs pulses, as the anti-backlash pulse
is inserted to ensure that there is no dead-zone (this minimizes phase noise
and spurs). The anti-backlash pulse width is 2.9ns default and 1.5ns minimum
(set by ABP1 and ABP2 in the Reference Counter Latch). In general we recommend
using the higher delays (2.9 & 6.0 ns), but if your PFD frequency is large, you
may need to use the shorter delay.
If you haven’t already done so, I recommend you Download ADI SimPLL from
This simulation software for ADI synthesizer products will allow you to predict
and optimize the phase noise performance in your specific application.