ADE7761: Applying pulses to the system

Document created by analog-archivist Employee on Feb 23, 2016
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I've got a request from a customer, who uses ADE7761B in his application,
concerning the IC' tolerance to a short pulse interference. The application is
an energy meter and its schematic is in the attachment.
The customer performs the following test according to a Russian standard
30207-94 (IEC1036-90). Voltage bursts with a 2 kV amplitude and a 1-2 ns
duration are applied to the meter input. The meter must not have pulses on its
calibration output (CF pin of the IC) and the meter reading variations must not
exceed 0.01 kW. The test duration is 1 minute.
During the circuit test the customer is observing pulses on CF output and the
meter readings are increasing on 0.1 - 0.3 kW.
Could You give any recommendations how to overcome this problem.


Although many sensitive electronic components contain a certain amount of
protection on-chip, it is not possible, internally,  to protect against the
kind of severe discharge described below.
Another problem is that the effect of an ESD discharge is cumulative, i.e., a
device may survive an ESD discharge, but it is no guarantee that it will
survive multiple discharges at some stage in the future.
So 2 things have to be considered in your design  - Fast Transient Pulse & ESD.

Fast Transient Pulse

The biggest issue with the pulse is not its amplitude (which can be as high as
4 kV), but the high frequency content due to the fast rise times involved. Fast
rise times mean high frequency content, which allows the pulse to couple to
other parts of the system through stray capacitance, for example. Large
differential signals can be generated by the inductance of PCB traces and
signal ground. These large differential signals could interrupt the operation
of sensitive electronic components. Digital systems are generally most at risk
because of data corruption. Minimizing trace lengths and use of ground planes
reduces the susceptibility to these high frequency pulses. Analog electronic
systems tend to be affected only for the duration of the disturbance. As the
bandwidth of the analog sections tends to be limited, the effect of an EFT
event is reduced.

Another possible issue with conducted EFT is that the effects of the radiation
will, like ESD, generally be  cumulative for electronic components. The energy
in an EFT pulse can be as high as 4 mJ and deliver 40 A into a 50ohm  load. 
Therefore, continued exposure to EFT due to, for example, inductive load
switching, may have implications for the long-term reliability of components.
The best approach is to protect those parts of the
system that could be sensitive to EFT. 

These connection points should be protected. Some techniques for protecting the
system are to • Minimize bandwidth and • Isolate sensitive parts of the system.
The Anti ~alias circuit below is recommended.


The best approach is to eliminate or attenuate the effects of the ESD event
before it comes in contact with sensitive electronic devices. This holds true
for all conducted  electromagnetic disturbances.Very often, no additional
components are necessary to protect devices - although this is a precedence
that is dangerous.
With a little care, those components already required in the circuit can
perform a dual role. For example, the meter must be protected from ESD events
at those points where it comes in contact with the outside world, e.g., the
connection to the shunt. Here, the ADE7761 is connected to the shunt via two
LPFs (antialias fi lters), which are required by the ADC This RC filter can
also be enough to protect against ESD damage to CMOS devices.

Anti-alias Filter

However, some care must be taken with the type of components used. For example,
the resistors should not be wire-wound because the discharge will simply travel
across them. The resistors should also be physically large to stop the
discharge from arcing across the resistor. In this design, 1/8W SMD 1206
resistors were used in the antialias filters. Ferrite beads can also be
effective when placed in series with the connection to the shunt. A ferrite
choke is particularly effective at slowing the fast rise time of an ESD current
pulse. The high frequency transient energy is absorbed in the ferrite material
rather than being diverted or reflected to another part of the system.

The PSU circuit is also directly connected to the terminals of the meter.

Here, the discharge will be dissipated by the ferrite, the input capacitor
(C17), and the rectifi cation diodes D2 and D3. The analog input V2P is
protected by the large impedance of the attenuation network used for
calibration. Another very common low cost technique employed to arrest ESD
events is to use a spark gap on the component side of the PCB (see Figure 14).
However, since the meter will likely operate in an open air environment and  be
subject to many discharges, this is not recommended at sensitive nodes like the
shunt connection. Multiple discharges could cause carbon build up across the
spark gap, which could cause a short or introduce an impedance that will in
time affect accuracy. A spark gap was introduced in the PSU after the MOV to
take care of any very high amplitude/fast rise time discharges.