ADE7758: RESET Bit

Document created by analog-archivist Employee on Feb 23, 2016
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Regarding INTERRUPT STATUS REGISTER (0x1A) datasheet states: "This bit in the
STATUS or RSTATUS register is logic high for only one clock cycle after a reset
event."
Is there any way to catch RESET to understand that power is lower than 4V?

 

I checked with one of our designers on this. The Reset bit is latched in the
RSTATUS register. So, if a reset occurred and you read the RSTATUS register,
the Reset bit will be set. If you read the RSTATUS register again, the Reset
bit should be clear because by reading the RSTATUS register, you are clearing
and acknowledging the Reset.

On the ADE7758 we provide some power supply monitoring features like sag
detection and zero crossing timeout detection. Sag detection can be used to
tell if an analog voltage input has dropped to a user configurable level. Since
the power supply for the ADE7758 is usually generated from the line voltage,
this is a good early warning that the power supply might go down and that the
part could reset. The zero crossing timeout can be used to detect if a zero
crossing has not occurred on an analog voltage input for a user specified
amount of time. This is another indicator that a phase has dropped out. The
attached application note describes how to use these 2 power supply monitoring
features to detect phase dropout.

So if you want a good indicator of the chip power supply so you can know if
it's going to reset, try the sag and zero crossing timeout detection.

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