ADAU1966: If using a direct MCLK can I leave LF and PLLVDD pins disconnected?

Document created by analog-archivist Employee on Feb 23, 2016
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Regarding the PLL of ADAU1966, I intend to use a 48kHz FS with a
24.576MHz master clock. I can provide all the clocks to the ADAU1966.
Can I completely disable the internal PLL or do I still need to connect the
PLLVDD and LF circuits ?


As you are providing a direct MCLK, the Loop Filter components are not required
so you do not need them. The PLLVDD however, involves interfacing inside the
part to other areas. I have asked the designers about this and they have
confirmed that the PLVDD is related to the direct clocking of the part by MCLK
and so you do need to apply power to the PLVDD pin at all times.