AD9959: FSK modulation performance

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
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I did an experiment of AD9959EVB. System Clock is 500MHz, FTW0 = 10MHz, FTW1 =
10.1MHz, use P0 Pin to switch the DAC's output frequency.When the switching
time is 20us, then the DDS's output is like Figure 1. If the switching time is
2ms, then the DDS's output is Figure 2. The switching time longer, the
performance better.
So seems when DDS is used in Hop Frequency application, if the switching time
shorter, the output signal's performance is worse. For DDS's quick hop
frequency applications, do you have some advice which can increase the
performance of output signal?

 

Is the profile pin toggle rate synchronous to the SYNC_CLK. Meaning, is the
toggle rate and SYNC_CLK at an integer ratio.
If not, that should help some.
Note, the profile pin toggle rate directly impacts the modulation index. The
modulation index will impact how the energy is spread in the spectrum.

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