AD9956 linear sweep (no dwell disabled) has a glitch when the FTW0 is changed to a lower value after a ramp-up

Document created by analog-archivist Employee on Feb 23, 2016
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I peform a Linear Sweep with the no-dwell bit cleared (i.e. CFR1[16]=0). This
means that the ramp-up and ramp-down is controlled by PS0. With PS0 high, a
ramp-up is performed and with PS0 low a ramp-down is performed.
My lower frequency is 40Mhz (FTW0) and the upper is 50Mhz (FTW1) and I perform
a ramp-up. The output stays at 50Mhz and when I change the FTW0 to 30Mhz there
is a glitch on the output.
Is there a way to avoid this glitch?

 

I see the same issue on the AD9956 Evalboard using the following setup:

Ref_clk(RF_IN input on J1)=400Mhz, R=1, linear Sweep enabled, No Dwell cleared
(CFR1[16]=0)and CFR1[17]=1, RDFTW=FDFTW==763Hz and RSRR=FSRR=655,35uS

FTW0 (i.e. PCR0) =40Mhz
FTW1 (i.e. PCR1) = 50MHz

When I ramp-up to 50Mhz and want to change the PCR0 to 30Mhz and avoid a glitch
then I set RDFTW much higher than initial settings, say 500KHz, and it seems to
work. Just before performing the ramp-down, RDFTW can be set again to 763Hz and
no glitch is present.

On speaking with the Product-Line Engineer for the AD9956, unfortunately there
is no other way to get around this issue, other than changing the RDFTW as per
above.

Furthermore, if the linear sweep starting with FTW0=30Mhz and FTW1=50Mhz and
then FTW0 is changed to 40Mhz the glitch does not appear.  The criteria should
be that the "2nd FTW0 value" > "1st FTW0 value" in order to avoid the glitch.

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