Q1.Our design uses the two options described on datasheet page 30. I.e.
synchronizing with SYNC_IN and SYNC_CLK signals AND a single crystal driving
multiple (=16) AD9954s. Do you recommend using it this way?
2a.Datasheet section Synchronizing multiple AD9954s, wrote: … all units must
share a common clock source. Weve one clock source but it is not common, right?
Well it seems like that the original XTAL clock would be delayed by each
AD9954. Is this right? The internal PLL of the AD9954 cannot compensate for
2b.For an equal DAC output we should likely need to compensate for the REFCLK
delay at AD9954 further away from the XTAL in the phase offset word. Do you
3a.The alternative what comes to my mind is to use a PLL-based clock
distribution chip to have the reference clock aligned to each AD9954 chip. Do
you think this is a better idea? Do you think the headache described in 2b will
3b.In the case of using a clock distribution chip. Do expect the sole option of
synchronizing 16 AD9954s with SYNC_IN and SYNC_CLK signals will work?
A1. I would have my reservations about driving as many as 16 AD9954s with a
single crystal. For such a large number of devices I would be inclined to
consider a full clock distribution strategy, using perhaps our AD9510 and
AD9512 parts. The accumulated delay and jitter between parts number 1 and 16
may create additional issues that would be better avoided. The synchronization
arrangements look to be exactly what is described in the datasheet,
2.a and b See answer 1. The delay but more so the jitter will kill the system
3. I think that by directly clocking the AD9945 at the REFCLK frequency and by
connecting the SYNC_CLO to the SYNC_IN pins, you will obtain the best
performance and synchronization of all 16 devices.