AD9954: Spur at SYSCLK/4

Document created by analog-archivist Employee on Feb 23, 2016
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I have used AD9954 as a clock reference, but in the output of DDS, one spur
which frequency is N*Fxtal/4 (N is the PLL multiplier)exists, would you help me
how to eliminate this spur.

 

The frequency that you refer to is equal to the SYNC_CLK signal - which is
always SYSTEM CLOCK/4. Therefore the spur is likely to arise from
crosstalk/coupling between the SYNC_CLK signal and the DAC output.

If you don't need the SYNC_CLK signal you can disable the SYNC_CLK output by
writing to bit 1 in the control function register.

If you need the SYNC_CLK signal then you should
- minimise the capacitive load attached to the SYNC_CLK output
- re-examine the system grounding and power supply decoupling, to reduce as far
as possible the ground impedance and the power supply impedance at high
frequencies
- re-examine the system layout to ensure that SYNC_CLK output signal is not
routed close to the REFCLK signal (if the REFCLK is modulated by SYNC_CLK, this
can create spurs in the output signal)

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