ad9951: REFCLK input considerations

Document created by analog-archivist Employee on Feb 23, 2016
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The AD9951 has input clock, according to data sheet it can be operated by: 1.
Crystal 2. Single ended We need to know the follow: 1. The ref clock input what
type technology it is: LVTTL/LVCMOS/LVPECL/Other 2. What voltage levels is can
accept min/max 3. Should the incoming signal need to be sine wave or square?

 

This is one of those specifications that requires that we specify the part
around the way it interfaces to the outside world, not just its own
characteristics.

The input impedance is 1500 Ohms.
However, 95% of the time, customers will be transmitting the REFCLK signal down
a cable, a transmission line, a trace... Something.
When they do, we recommend that they 50-ohm terminate locally, just outside the
clock input pin, as we do on our evaluation board.

Specifying the REFCLK input voltage in dBm is an effort to convey to the
customer what oscillator strength they need back up at the front end of the
transmission line.
In short, we're looking for the user to have a maximum of 900mV pk-pk swing at
the REFCLK input.

The AD9951 reference input is normally driven with a sine wave.
It is AC  coupled (with a capacitor) and if a single-ended drive is used the
other  clock input is decoupled with another capacitor.
The drive level must  not be over 1.8 V pk-pk (0.64 V r.m.s.) with a 1.8V
supply, but may be  as low as 100 mV r.m.s.
However it is better to use as large a drive as  possible to minimise phase
noise.

If you drive the reference input with a square wave it must have a duty  cycle
of close to 50% and logic levels (for 1.8V supply) of logic 0<.4V  and logic
1>1.25V.
If you use the PLL clock multiplier with logic inputs  the duty cycle may be
slightly worse - between 35% and 65%.

Driving differentially is more recommended. Better common mode rejection is
achieved. 

However, two things to be careful about

- Common mode level of the AD9951 input :

The differential inputs are biased around 1.35V which is different from the
common mode level of LVPECL outputs.
Probably best therefore to AC-couple the clock (using series capacitors) if
using  ICS8432-101 3.3V LVPECL Frequency Synthesizer or similar.

-Jitter of the output :

You might consider using a crystal with e.g. our AD9540 clock generator, which
has <700fs clock jitter.
Otherwise, a low jitter XTAL oscillator (e.g. sinewave output) of appropriate
amplitude will provide good performance.

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