AD9912: multichip synchronization

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
Version 2Show Document
  • View in full screen mode

I hope to synchronize 32 pcs AD9912. But when we test with only 2 pcs of
AD9912, the difference of output phase are variable each time after power on. I
disabled the  CLK multiplier and provided 1GHz clock external, the update
clocks are also synchronized. How can I synchronize output phase of AD9912?


Multiple AD9912s can be synchronized however there's setup and hold times that
need characterizing.
I have started an initial application note that addresses how to synchronize
but again the timing has not been characterized.
Please see the attachment.