AD9874: Test registers

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

Our customer has some problems with TEST REGISTERS (0x37 ... 0x3E). The AD9874
functionality depends on status of these registers, and they worked with these
bits using hit-and-miss method, but now they want to get detailed description
of these registers.


Page 14 of the datasheet gives a description of the test registers and the SPI
port read enable function. The test registers as stated are not to be used,
they are reserved for a factory test mode. Do not write to test registers. If
you do need to write to test registers (e.g. in case of a sequential write of
all on-chip registers) then only write back the default values given in table 1
of the datasheet on pages 13/14.

The following bits have other functions:
0x3A bit 3 enable read from SPI
0x3B bit 3 has a tristate DOUTB function

The function of both bits are described in the following section from the
datasheet (page 15, Serial port interface):

The serial port of the AD9864 has 3-wire or 4-wire SPI capability, allowing
read/write access to all registers that configure the device's internal
parameters. The default 3-wire serial communication port consists of a clock
(PC), peripheral enable (PE), and bidirectional data (PD) signal. The inputs to
PC, PE, and PD contain a Schmitt trigger with a nominal hysteresis of 0.4 V
centered about the digital interface supply, i.e., VDDH/2. A 4-wire SPI
interface can be enabled by setting the MSB of the SSICRB register (Reg. 0x19,
Bit 7) and setting Reg. 0x3A to 00, resulting in the output data appearing on
the DOUTB pin.
Page 16 of datasheet states in relation to the use of this bit:
Note that since the default power-up state sets DOUTB low, bus contention is
possible for systems sharing the SPI output line. To avoid any bus contention,
the DOUTB pin can be three-stated by setting the fourth control bit in the
three-state bit (Reg. 0x3B, Bit 3). This bit can then be toggled to gain access
to the shared SPI output line.

For further information see page 14 of the datasheet.