QLooking into executing readback from this device. Is the data readback from the
Buffer or Register memory? Can the device output be disabled for the entirety
of the readback, if so how? Regarding the datasheet, what exactly does the dds
core consist of?
AThe data is read back from the buffer memory. All interactions by an external
processor with the device registers (read or write) are with the buffer memory.
The internal registers are updated from the buffer memory on an FUD signal.
There is no simple disable function on the device. You can setup one of the
profiles with a frequency of 0Hz and a particular phase offset, to get the
device to output a DC level when you switch to that profile. You have to select
On page 15 of the datasheet, the DDS core is described as the part of the
device which converts the parameter settings (frequency, phase, etc) into the
samped data which is fed into the DAC. However the term DDS core can refer to
the active registers which dictate the current frequency which is being
generated, as opposed to the buffer registers which are being accessed by the