QI have two questions for AD9854. 1) I will use external clock for DDS. Can I
left open (or tie to gnd) the PLL filter pin no. 61. Of course, PLL will be
disabled. 2) The same question for comparator pins 36,42 and 43 and for DAC2,
pins 51 and 52.
AI think it's good practise (1) to design-in for the PLL filter, and yet you
still can disable the PLL. see fig 64, datasheet rev E.
(2) for output pins it can be left floating/unconnected, but for input it must
be connect e.g pin 42, 43 else you have issues.