AD9854: Time between rising edge of UDCLK and the start of the waveform

Document created by analog-archivist Employee on Feb 23, 2016
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application works fine, but 1 question : how much time is there between the
rising edge of udclk and the start of the waveform?

 

In order to determine how much time there is between the rising edge of I/O
Update CLK and the start of the waveform, you should refer to the "Pipeline
Delays," section on page 4 of the data sheet and add up the system clock cycles
(fixed delays) that are associated with the functional blocks that are
employed. All the delays will be additive to the 3 Sys Clk Cycles (this will
not be instantaneous due to the transfer from the I/O Port Buffers to the
Programming Registers) associated with the I/O Update Clk (External Mode).
Reading the "Notes" section on page 5 (in this case Notes 4, 5 & 6) should help
your understanding of the pipeline delays and how some delays can be bypassed.

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