AD9854_FSK toggle rate

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

I want to implement 10Mbps FSK modulation by using DDS.
However, I looked at the AD9854 datasheet, the pipeline delay for the DDS core
is 33 SYSCLK. If the clock is 300MHz, the delay is about 110nS which is around
a modulation period for 10Mbps FSK. Is it OK for 10Mbps FSK modulation?
If AD9854 can not do it, can you recommend some part or solution which can do
10Mbps modulation?

 

The AD9854 could do this. Most all our DDS can run higher that 10Mbps for FSK.
Note, pipe line delay of 33 system clock periods does not limited the FSK max
toggle rate.
The max FSK toggle rate, I believe, is 1/2 of the system clock rate, so that
way faster than 10Mbps.

Attachments

    Outcomes