AD9854: Sequence for writing new data to the programming registers

Document created by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

I am working with the dds ad9854 and i have some questions

there is a port i/o update for programming register to transfer the new loaded
data into the dds core.
Does the control register (at 1D-20 add) need also a i/o update pulse to
transfer the new mode of operation(in example) into the dds core, does the
control register have also double buffer as the programming registers?

Is there any sequence of writing the new data to the programming
registers when changing the mode of operation?

Do you have a suggested sequence of writing to the dds add
for chirp mode and step freq mode?

Do you have an application nte in this issue timming of dds and
addressing the new data?


As far as I can see, the control registers are written to and read from in the
same way as the other registers in Table V. A valid IO update event is required
to transfer data from the buffer memory into the register banks. The control
register banks are the same as any other register banks in that data written
to   the register is held in a buffer until a valid IO update event occurs
(either an internal update or a rising edge on the I/O UD pin.

There is no particular recommended sequence. However, one point to bear in mind
is the point made at the bottom left of pg 29 in the datasheet in the section
entitled "Notes on Serial Port Operation".

If the part is being programmed in serial mode and the serial configuration
bits had previously been changed but were still in the IO buffer memory, the
operation of the serial interface will change when an IO update event occurs
(either an internally generated I/O update or an externally applied rising edge
at the I/O UD pin) and the contents of the buffer memory is loaded into the
register banks. If, in addition,  the part is operating in internal update
mode, the user has no control over exactly when this update event occurs. In
the case where a serial multibyte transfer is in progress when the update event
occurs, the transfer might be disrupted. (e.g. if  the serial mode was changed
from MSB first to LSB first in the middle of a serial transfer).

This potential situation would suggest that you apply an external update pulse
after any write to the control register which changed the serial port
configuration. In this way you directly determine when the control register is
updated, and eliminate the risk that an I/O update occurs in a multibyte
transfer at some future time.

There is nothing recommended in the datasheet. Obviously, you should set up the
frequency tuning words, ramp rates etc before switching modes so that when the
mode is changed, you know exactly what will happen. This is just normal a
normal habit of initialising registers before you use them.

All the dds application notes are on the Analog Devices website. Look under