AD9840A: clock rate

Document created by analog-archivist Employee on Feb 23, 2016
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-In the Datasheet for the AD9840A on page 3 is a MAXIMUM CLOCK RATE of 20 MHz
specified over ruling f-SHP of max. 40MHz. What is the meaning of
this clock?

-On page 7 a detail drawing of CCDIN (Pin 30) is shown but the values for the
input
impedance are missed. Can you specify that please? Is this input buffered or are
there any dynamik effects?

-On page 5 t-SHP and t-SHD are given but not in the timing diagram. Affects it
the
low or high level state?

-Order of sampling clocks edges on page 5 are specified from SHP to SHD but not
opposide. Is this not critical?

 

-In the Datasheet for the AD9840A on page 3 is a MAXIMUM CLOCK RATE of 20 MHz
specified over ruling f-SHP of max. 40MHz. What is the meaning of this clock?
This is a typo. The max clock rate should be 40 MHz, the same as it is listed
everywhere else in the specs. Sorry for the confusion.

-On page 7 a detail drawing of CCDIN (Pin 30) is shown but the values for the
input impedance are missed. Can you specify that please? Is this input buffered
or are there any dynamik effects?
We don't supply exact values for these on the data sheet. Approximate values
are R ~ 100 ohms and C ~10 pF. Dynamic effects are minimal- this input is
easier to drive than a traditional switched-cap input ADC.

-On page 5 t-SHP and t-SHD are given but not in the timing diagram. Affects it
the low or high level state?
The pulse widths are for the (active) low time, since the signals are shown as
25% duty cycle in the timing diagram. Active low polarity is the default state
of these products. The Control Register may be programmed to change the inputs
to active high.

-Order of sampling clocks edges on page 5 are specified from SHP to SHD but not
opposide. Is this not critical?
The SHD to SHP time is indeed less critical, and in practice the CCD signal
prevents the SHD pulse from getting close to the next SHP pulse. We've never
had a problem with this in an application.
It is critical that user provides appropriate clocks which are synchronized to
the black level and pixel level of the CCD signal. It is likely that that the
timing of the CCD signal will be the main factor in determining the actual
timing of SHP and SHD. The DATACLOCK rising edge should then be placed between
the rising edge of SHD and the falling edge of SHP while the respecting the
inhibit time t-INH.

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