AD9777 max speed and timing query (SR#: 1200982)

Document created by analog-archivist Employee on Feb 23, 2016
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using AD9777 in 2 port mode on 120 MHz. Data and clock is fed by a FPGA to the
DAC.

According to the datasheet this should be possible to use 120MHz both with pll
enable and disable (read from
table 11 in datasheet). But according to the figure 55 data has to be stable
tOD+tH6.5ns+3.2ns=9.7ns ie
more than a period = 8.33 ns so how could this work.?

Then we changed to set the PLL enable. And our problem then is when we use the
PLL the data out is not correct. I have pictures of the timing.

 

At 120Mhz CLKIN the clock period is 8.3333ns as stated below. from reading of
figure 55 is that data must be valid for at least 6.5ns. Data needs to go high
5.0ns before DATACLOCK (not CLKIN) goes high. The hold time is -3.2ns meaning
that data can go low 3.2ns before DATACLK goes high. DATA can change 5.0ns
before DATACLK goes high, then change 8.333ns later and meet the spec.

Figure 55 applies to Two Port Mode, PLL disabled. 

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