AD9767: Input timing for interleaved mode

Document created by analog-archivist Employee on Feb 23, 2016
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This is to verify AD9767 functionality in interleave mode. 

Figure 27 on page 15 of Rev C datasheet contains interleave block diagram. 

Could you please confirm that Port1,2 input latches are NOT synchronized with
IQCLK? 

Prior to starting my HW design, I need to be sure that data to the chip can be
delivered to the input latches upon rising edge of IQWRT strobe signal with no
clock support. 

 

The block diagram clearly shows that IQWRT and IQSEL that control the port 0
and port 1 latches in interleaved mode.

However there is some constraint on the timing of IQCLK with respect to IQWRT
(because the port latches need sufficient time to aquire  the input data and
settle, in order that the DAC latches see stable data.

This constraint is that you must drive an IQCLK rising edge before or
simultaneously to the rising edge that you drive on IQWRT. Otherwise, the data
clocked in on the previous IQWRT will not be reliably latched into the DAC
latches. There follows a 2ns keep out window for the IQCLK rising edge during
which data will not be reliably latched into the DAC latches. After this 2.0ns
window, the next data will be latched into the DAC.

This is explained in the "Dual port mode" timing section and shown in figure
25. The same restriction applies in interleaved mode and in Dual Port mode.

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