Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
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1, I am using  four AD9734s. Because DACCLK is divided by 2 to create
DATACLK_OUT, the phase of DATACLK_OUT can be 0° or 180°, it's uncertain. As the
red line shown (attache figure 1), the DATACLK_OUT is also used to transit the
incoming data to the DACCLK domain. So for multiple AD9734s, even though their
DATACLK_INs and DACCLKs have the same phase, because of the Dac Sampling
Signal's(Red line) uncertainty of different AD9734s, the sequence of feeding
D1A and D2A into DAC CORE is different. So multiple AD9734s' DAC output can't
be synchronized, that is, compared to other DAC's output, some DAC' output may
lag one DACCLK.
2, Also,I found another problem: after I configured the MODE REGISTER (0x00)and
FSC(0x02,0x03), the timings of multiple DAC output may be variable. For
example, before writing register, the first three DAC output is good and the
fourth DAC output lags one DACLK, but after writing registers, the first two
DAC output is OK and the third and fourth DAC output lags one DACCLK. Whether
the operation to register can make influence to the DACCLK?
Would you please give me some advices about the two problems?


The AD9734 has two internal timing domains. The first domain is the digital
inputs which are clocked by the DATA_CLK_IN. The second domain is where the DAC
actually gets a clock from the DAC_CLK_IN. These domains run independently and
there is no required timing relationship (no set up and hold requirement)
between the DATACLK_IN and DAC_CLK_IN. The key to the input domain handing off
the digital data to the DAC domain is that there is an internal FIFO that
automatically makes up for any phase difference between DATACLK_IN and
DAC_CLK_IN. The big issue with this is that anytime the DAC powers up, the FIFO
can come up in one of several valid different states, all of which cause a
different delay from the digital inputs to the DAC output. I'm sure this is why
you are seeing the problem.

The FIFO can be turned off, but when it is turned off, then there are timing
requirements that must be met between DATACLK_IN and DAC_CLK_IN. These timing
requirements are given in table 28 on page 55 of the AD9734 rev A datasheet.

The solution that we have recommended in the past for synchronizing multiple
AD9734s is that a special circuit must be built in the FPGA/digital driver.
This circuit takes the DATACLK_OUT from the first AD9734 and uses it to sample
the DATACLK_OUT signals from all of the other AD9734s. If it detects that any
of the DATACLK_OUT signals are inverted from the first one, then it
automatically inverts the DATACLK_IN for that AD9734. In this way, strict
timing relationships can be achieved between the DATACLK_OUT, DATACLK_IN and
DACCLK on all AD9734s.