QWhat’s so special about JESD204B? About Subclass 1?
AJESD204B is the latest iteration of the JEDEC JESD204 specification for SERDES
transmission of high-speed data between mixed signal devices (such as ADCs and
DACs) and digital processors such as DSP chips, FPGAs or digital ASICs. The
single 5.0GBPS lane per ADC channel greatly simplifies high-speed board design,
due to the reduction in the number of high speed traces as well as the
embedding of the clock in the data for an asynchronous transfer. Subclass 1
devices take advantage of a system-wide master timing reference known as
“SYSREF” which allows users to achieve deterministic latency on all devices in
the system in a robust and straightforward way. Q5.