AD9512 Phase setting not working

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
Version 1Show Document
  • View in full screen mode

We have a problem setting up the AD9512. We have set to clock divider to 5, and
should therefore be able to change the phase delay to 0,1,2,3,4.
But we can’t see any changes at all when scoping this.
Schematics and SW setup is attached.

--
On the first output we are using divider = 5, so it means we do have 5 choices
of shifting the phase. The problem is that even applying changes to the
registers (tried all 5 values out) and successfully reading register value back
those changes are not visible on the oscilloscope.
In mean time we are able to change output's amplitude & divider ratio and those
changes are clearly visible on the oscilloscope. For the first two outputs we
have the same divider ratio applied. So we are able to compare signals at the
same time if something changes, but unfortunately it doesn't...

Do we need to update some special bit in correct register in order to see
changes for phase offset?

We manage to set the divider and amplitude, but somehow we cannot see any
change in the output when setting the phase offset value (on output 0 and 1).
We measure by looking at two outputs (0 and 1) from the clock-divide (They both
have the same divider value).
What can be the error?

The register writing is as follows (always 3 byte, control byte + 2 data bytes,
default MSB mode):

                instr_table[tab_size++] = (LVDS_1_REG_ADDR |
AD9512_BTC_2_BYTES) << 16
                                                                               
| /*LVDS_0_TO_2_REGS_VALUE*/lvds_1 << 8 |
/*LVDS_0_TO_2_REGS_VALUE*/lvds_0;              // LVDS_1_REG_ADDR &
LVDS_0_REG_ADDR
                instr_table[tab_size++] = (LVDS_3_REG_ADDR |
AD9512_BTC_2_BYTES) << 16
                                                                               
| LVDS_3_TO_4_REGS_VALUE << 8 | /*LVDS_0_TO_2_REGS_VALUE*/ lvds_2; //
LVDS_3_REG_ADDR & LVDS_2_REG_ADDR
                instr_table[tab_size++] = (REG_ADDR_AFTER_LVDS_4 |
AD9512_BTC_2_BYTES) << 16
                                                                               
| LVDS_3_TO_4_REGS_VALUE; // REG_ADDR_AFTER_LVDS_4 = 0 & LVDS_4_REG_ADDR
                // CLK1 and CLK2
                instr_table[tab_size++] = (AD9512_CLK1_CLK2_REG_ADDR |
AD9512_BTC_1_BYTE) << 16 | AD9512_CLK1_CLK2_REG_VALUE << 8;  // CLK1_CLK2

                // Setting LVDS Outputs Phase based on the input parameters, if
not changed, set to 0
                if(LVDS_0_PHASE_VALUE != 0x00)
                                printk("AD9512 | LVDS_0_PHASE_VALUE has been
changed to hex = 0x%X | dec = %d\n", LVDS_0_PHASE_VALUE, LVDS_0_PHASE_VALUE);
                if(LVDS_1_PHASE_VALUE != 0x00)
                                printk("AD9512 | LVDS_1_PHASE_VALUE has been
changed to hex = 0x%X | dec = %d\n", LVDS_1_PHASE_VALUE, LVDS_1_PHASE_VALUE);
                if(LVDS_2_PHASE_VALUE != 0x00)
                                printk("AD9512 | LVDS_2_PHASE_VALUE has been
changed to hex = 0x%X | dec = %d\n", LVDS_2_PHASE_VALUE, LVDS_2_PHASE_VALUE);
                if(LVDS_3_PHASE_VALUE != 0x00)
                                printk("AD9512 | LVDS_3_PHASE_VALUE has been
changed to hex = 0x%X | dec = %d\n", LVDS_3_PHASE_VALUE, LVDS_3_PHASE_VALUE);
                if(LVDS_4_PHASE_VALUE != 0x00)
                                printk("AD9512 | LVDS_4_PHASE_VALUE has been
changed to hex = 0x%X | dec = %d\n", LVDS_4_PHASE_VALUE, LVDS_4_PHASE_VALUE);

                // DIVIDERS | Setting up LVDS Outputs & Phase | Divider = 5
                instr_table[tab_size++] = (LVDS_0_DIV_PHASE_ADDR |
AD9512_BTC_2_BYTES) << 16 | LVDS_0_PHASE_VALUE << 8 |
LVDS_0_DIVIDER_VALUE;     // PHASE = 0 & LVDS_0_DIV_ADDR = DIV5
                instr_table[tab_size++] = (LVDS_1_DIV_PHASE_ADDR |
AD9512_BTC_2_BYTES) << 16 | LVDS_1_PHASE_VALUE << 8 |
LVDS_1_DIVIDER_VALUE;     // PHASE = 0 & LVDS_1_DIV_ADDR = DIV5
                instr_table[tab_size++] = (LVDS_2_DIV_PHASE_ADDR |
AD9512_BTC_2_BYTES) << 16 | LVDS_2_PHASE_VALUE << 8 | LVDS_2_DIVIDER_VALUE
/*LVDS_CHOOSEN_DIV_MK1*/;   // PHASE = 0 & LVDS_2_DIV_ADDR = DIV5, changed to
DIV10 - Henning
                instr_table[tab_size++] = (LVDS_3_DIV_PHASE_ADDR |
AD9512_BTC_2_BYTES) << 16 | LVDS_3_PHASE_VALUE << 8 |
LVDS_3_DIVIDER_VALUE;     // PHASE = 0 & LVDS_3_DIV_ADDR = DIV30
                instr_table[tab_size++] = (LVDS_4_DIV_PHASE_ADDR |
AD9512_BTC_2_BYTES) << 16 | LVDS_4_PHASE_VALUE << 8 |
LVDS_4_DIVIDER_VALUE;     // PHASE = 0 & LVDS_4_DIV_ADDR = DIV14

                // Do Soft Sync AND set function pin to SyncB
                instr_table[tab_size++] = (LVDS_FUNTION_REGISTER_ADDR |
AD9512_BTC_1_BYTE) << 16 | (LVDS_SOFT_SYNC_FUNTION_REGISTER_VALUE |
LVDS_SYNCB_FUNTION_REGISTER_VALUE) << 8;      // Soft SYNC bit

                instr_table[tab_size++] = (LVDS_FUNTION_REGISTER_ADDR |
AD9512_BTC_1_BYTE) << 16 | LVDS_SYNCB_FUNTION_REGISTER_VALUE <<
8;              // Reset Soft SYNC bit
               
                //Update Registers
                instr_table[tab_size++] = (LVDS_UPDATE_REGISTERS_ADDR |
AD9512_BTC_1_BYTE) << 16 | LVDS_UPDATE_REGISTERS_VALUE << 8;               //
Update REGS

 

In order to see a change on the phase, they need to issue an output sync. This
can either be done as a hardware sync using the SYNCB function or issuing a
software sync using Register 0x58<2>.

The exact sequence for a soft sync is:
R0x58=0x04  ; stalls the outputs
R0x5A=0x01 ; update the live registers so that the write to 0x58 takes effect.
R0x58=0x00 ; releases the outputs.
R0x5A=0x01; ; update the live registers so that the write to 0x58 takes effect.

Outcomes